1. Technical Field
The present invention relates to an image processing device performing an error diffusion process.
2. Related Art
The error diffusion process is used to express multi-gradation image data in less gradations, for example, when a gradation value of a pixel is binarized, the error diffusion process is realized in a manner in which a process of diffusing an error of the gradation value occurring when performing the binarization to peripheral pixels of a target pixel is performed on the pixels of the image data. When the error diffusion process is performed for each line of the image data, the process of diffusing the error is performed in order from a pixel of one end of a certain line to the a pixel of the other end as the target pixels, and the process is performed from the first line to the last line.
In this case, the error of the target pixel of the N-th line is diffused to pixels present in the (N+1)-th line. Accordingly, the diffusion of the error of the N-th line with respect to a pixel in the (N+1)-th line is completed, after which this pixel is set as the target pixel until there is no longer a possibility that the error will be diffused to this pixel, whereby there is a limitation in that it is difficult to perform the error diffusion process of the (N+1)-th line. In the related art, a technique for performing the error diffusion process at a high speed under such a limitation has been developed, for example, in JP-A-2000-125122, a technique is described in which a parallel process of performing an error diffusion process of adjacent lines by a first CPU and a second CPU is performed, and the error diffusion process is performed in parallel while sequentially checking a positional relationship of the target pixel for each pixel such that the error diffusion process of the (N+1)-th line does not pass the error diffusion process of the N-th line.
In JP-A-2000-125122, the positional relationship of the target pixel is sequentially checked for each pixel such that the error diffusion process of the (N+1)-th line does not pass the error diffusion process of the N-th line. Accordingly, it is necessary to perform the checking whenever the target pixel is changed for all the pixels present in each line. For this reason, the time necessary for the checking is too long to be ignored, and the effect of the high speed according to the technique of the related art is attenuated as the number of pixels is increased. In a processor of performing a great number of parallel processes, a configuration of performing an operation such that a process determined in advance on the basis of an input value provided when starting the process is performed to obtain an output value is employed, and it is difficult to provide a new input value by interrupting the process in the course of the operation. Accordingly, in the configuration of performing the error diffusion process for each line while checking the progress for each line whenever the target pixel is changed using a plurality of such processes, even when complete parallelization is attempted, it is difficult to control the progress degree of one processer on the basis of the input value representing the progress of the other processor, and in practice, it is difficult to perform complete parallelization.